Spin-Torque Transfer Magneto-Resistive Memory Architecture

ABSTRACT

A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT E ) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT 0 ) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.

FIELD OF INVENTION

The present invention relates to spin-torque transfer magneto-resistive random access memory (STT MRAM) devices.

DESCRIPTION OF RELATED ART

Spin-torque transfer magneto-resistive random access memory (STT MRAM) devices provide fast access time, low cost, high density, and non-volatility. A STT MRAM device provides a magnetization switching scheme that does not use a magnetic filed for orientating the relative magnetism of the device.

Data is written to memory cells of the device by using a spin-polarized current to change the orientation of the magnetization of a magnetic layer in a tunnel magneto-resistive element. The spin-polarized current includes electrons with a majority of electrons having a particular spin and may be induced by passing current through a magnetic layer of a device.

It is desirable for a device to minimize power consumption while maintaining a dense arrangement of cells.

BRIEF SUMMARY

In one aspect of the present invention, a memory array device includes a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT_(E)) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT₀) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.

In another aspect of the present invention, memory system includes a processor and a memory array communicatively connected to the processor, the memory array includes a first memory cell including a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT_(E)) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell including a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT₀) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.

A method for operating a memory array device includes initiating a write “0” state in the device, wherein the initiating the write “0” state includes inducing a first voltage in a word line of the device, and inducing a second voltage in a first bit line (BLT_(E)) of the device.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates an example of a single bit line memory array.

FIG. 2 illustrates an example of a cell of the single bit line memory array of FIG. 1.

FIG. 3 illustrates an example of a double bit line memory array.

FIG. 4 illustrates an example of a cell of the double bit line memory array of FIG. 2.

FIG. 5 illustrates an exemplary embodiment of a hybrid bit line memory array.

FIG. 6 illustrates an exemplary embodiment of cells of the hybrid bit line memory array of FIG. 5.

FIG. 7 illustrates a block diagram of a memory system.

FIG. 8 illustrates a timing diagram including states of the single bit line memory array, the double bit line memory array, and the hybrid bit line memory array.

FIG. 9 illustrates a side cut-away view of an example of a magnetic tunnel junction device.

DETAILED DESCRIPTION

FIG. 1 illustrates an example of a single bit line (SBL) memory array 100. The array 100 includes a source line (SL) arrangement 102, a word line (WL) 104, and a plurality of bit lines (BL) 106 connected to cells 108. FIG. 2 illustrates an example of a cell circuit diagram for a cell (memory sub-array) 108 of the single bit line memory array 100. The cell 108 includes a field effect transistor (FET) 202 with a source terminal connected to the source line arrangement 102, a gate terminal connected to the word line 104, and a drain terminal connected to a magnetic tunnel junction device (MTJ) 204. The magnetic tunnel junction device 204 is connected to the bit line 106. The source terminals of the each of the FETs 202 in the cells 108 are connected to the source line arrangement 102. The source line 102 capacitance and resistance is large compared to the capacitance and resistance of the bit lines 106. In operation, unselected bit lines 106 consume power to avoid applying writing voltage across the MTJ 204 resulting in an undesirable disturb situation. A disturb situation may, for example, include an unintentional change in a state of cells 108. For example, it may be desirable to change a state of one cell 108 in the array 100 to a “1” state. In some instances, a MTJ 204 of another cell 108 may change states due to a voltage that may be present across the MTJ 204 since the cells 108 are connected to a common source line 102 in the array 100. The MTJ device 204 may include, for example, a fixed magnetic layer, a dielectric tunnel barrier, and a free magnetic layer. Data is written to the device by changing the magnetic orientation of the free magnetic layer using spin polarized current. Data may be read from the device by using, for example, parallel direction reading and anti-parallel direction reading.

FIG. 3 illustrates an example of a double bit line (DBL) memory array 300. The array 300 includes bit line compliments (BLC) 302, a word line 304, and bit lines true (BLT) 306 connected to cells 308. FIG. 4 illustrates an example of a cell circuit diagram for a cell 308 of the double bit line memory array 300. The cell 308 includes a FET 402 with a source terminal connected to the BLC 302, a gate terminal connected to the word line 304, and a drain terminal connected to a magnetic tunnel junction device 404. The magnetic tunnel junction device 404 is connected to the BLT 306. In the illustrated example, the independent bit lines BLC 302 and BLT 306 allow the unselected cells to function properly when the voltage of the bit lines of the unselected cells are the same. This arrangement reduces power consumption; however the cell size may be relatively larger due to the use of two bit lines.

FIG. 5 illustrates an exemplary embodiment of a hybrid bit line (HBL) memory array 500. The array 500 includes a plurality of cells (memory sub-arrays) 508 (508 a and 508 b) that are connected to a first bit line (bit line true even (BLT_(E))) 505, a second bit line (bit line true odd (BLT₀)) 506, a bit line compliment (BLC) 502, and a word line (WL) 504. FIG. 6 illustrates an exemplary embodiment of the cells 508 a and 508 b. In this regard, the cell 508 a includes a FET 602 a that may include an nFET or pFET device having a source terminal connected to the BLC 502 at a node 601, a gate terminal connected to the word line 504 at a node 603 and a drain terminal connected to a magnetic tunnel junction (MTJ) device 604 a that is similar to the MTJ devices described above, including, for example, a fixed magnetic layer, a dielectric tunnel barrier, and a free magnetic layer (not shown). The MTJ device 604 a is connected to the BLT_(E) 505 at node 605. The cell 508 b is similar to the cell 508 a and includes a FET 602 b having a source terminal connected to the BLC 502 at the node 601, a gate terminal connected to the WL 504 at the node 603, and a drain terminal connected to a MTJ device 604 b. The MTJ device 604 b is connected to the BLT₀ 506 at the node 607.

FIG. 7 illustrates a block diagram of a system 700 including a processor 702 connected to the memory array 500. In operation, the processor 702 is operative to control the voltages of the lines 505, 506, 502, and 504 to change the states of cells 508 in the array 500.

FIG. 8 illustrates a timing diagram that includes operating states for the SBL memory array 100 (of FIGS. 1 and 2), the DBL memory array 300 (of FIGS. 3 and 4), and the HBL memory array 500 (of FIGS. 5 and 6). The horizontal axis represents time (t) while the vertical axis represents voltage (v).

In this regard, for the SBL memory array in a write “0” state, the bit line (BL) voltage is high (e.g., 2.2-5.5 volts) and the source line (SL) voltage is low (e.g., 0 volts). In a write “1” state, the SL voltage is high and the BL voltage is low. In a read state, the SL voltage is low and the BL voltage is greater than 0, but less than the high voltage. The diagram illustrates the drive time in the write “1” state for the SL is relatively long resulting in a long cycle time.

Referring to the DBL memory array, in a write “0” state, the BLT voltage is high and the BLC voltage is low. In the write “1” state, the BLC voltage is high and the VLT voltage is low. In the read state, the BLC voltage is low and the BLT voltage is greater than 0 but less than the high voltage. The BLC drive time is reduced relative to the SL drive time of the SBL memory described above.

In an exemplary method for operating the HBL array 500 (of FIG. 5), in the write “0” state, the word line voltage is high, the BLT_(E) voltage is high, the BLC voltage is low, and the BLT₀ voltage is low. In the write “1” state, the word line voltage is high, the BLT_(E) voltage is low, the BLC voltage is high, and the BLT₀ voltage is high. In the read state, the word line voltage is high, the BLT_(E) voltage is greater than 0 but less than the high voltage, the BLC voltage is low, and the BLT₀ voltage is low. In the write “1” state, the drive time for the BLC and BLT₀ is relatively shorter than the drive time for the write “1” state of the SBL array 100 (of FIG. 1).

FIG. 9 illustrates a side cut-away view of an example of a MTJ device similar to the MTJ device 604 described above. In this regard, the MTJ device 604 includes a thin dielectric tunnel barrier 902 disposed between a free magnetic layer 904 and a fixed magnetic layer 906. In the illustrated embodiment, the free magnetic layer 904 is connected to the node 605, and the fixed magnetic layer 906 is connected to the FET 602.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described. 

What is claimed is:
 1. A memory array device comprising: a first memory cell comprising: a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT_(E)) and a second terminal; and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device; and a second memory cell comprising: a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT₀) and a second terminal; and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
 2. The device of claim 1, wherein the first magnetic tunnel junction device includes a dielectric tunnel barrier layer disposed between a free magnetic layer and a fixed magnetic layer.
 3. The device of claim 1, wherein the first field effect transistor is an nFET device.
 4. The device of claim 1, wherein the second field effect transistor is an nFET device.
 5. The device of claim 1, wherein the first memory cell and the second memory cell of the device are operative to enter a write “0” state when a voltage is applied to the word line and the first bit line (BLT_(E)).
 6. The device of claim 1, wherein the first memory cell and the second memory cell of the device are operative to enter a write “1” state when a voltage is applied to the word line, the second bit line (BLC), and the third bit line (BLT₀).
 7. The device of claim 1, wherein the first memory cell and the second memory cell of the device are operative to enter a read state when a voltage is applied to the word line and the first bit line (BLT_(E)).
 8. The device of claim 7, wherein the voltage applied to the first bit line (BLT_(E)) in the read state is less than a voltage applied to the first bit line (BLT_(E)) in a write “0” state.
 9. A memory system comprising: a processor; and a memory array communicatively connected to the processor, the memory array comprising: a first memory cell comprising: a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT_(E)) and a second terminal; and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device; and a second memory cell comprising: a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT₀) and a second terminal; and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
 10. The device of claim 9, wherein the first magnetic tunnel junction device includes a dielectric tunnel barrier layer disposed between a free magnetic layer and a fixed magnetic layer.
 11. The device of claim 9, wherein the first field effect transistor is an nFET device.
 12. The device of claim 9, wherein the second field effect transistor is an nFET device.
 13. The device of claim 9, wherein the first memory cell and the second memory cell of the device are operative to enter a write “0” state when a voltage is applied to the word line and the first bit line (BLT_(E)).
 14. The device of claim 9, wherein the first memory cell and the second memory cell of the device are operative to enter a write “1” state when a voltage is applied to the word line, the second bit line (BLC), and the third bit line (BLT₀).
 15. The device of claim 9, wherein the first memory cell and the second memory cell of the device are operative to enter a read state when a voltage is applied to the word line and the first bit line (BLT_(E)).
 16. The device of claim 15, wherein the voltage applied to the first bit line (BLT_(E)) in the read state is less than a voltage applied to the first bit line (BLT_(E)) in a write “0” state.
 17. A method for operating a memory array device, the method including initiating a write “0” state in the device, wherein the initiating the write “0” state includes: inducing a first voltage in a word line of the device; and inducing a second voltage in a first bit line (BLT_(E)) of the device.
 18. The method of claim 17, wherein the method further includes initiating a write “1” state in the device, wherein the initiating the write “0” state includes: inducing the first voltage in the word line of the device; inducing the second voltage in a second bit line (BLC) of the device; and inducing the second in a third bit line (BLT₀) of the device.
 19. The method of claim 17, wherein the method further includes initiating a read state in the device, wherein the initiating the read state includes: inducing the first voltage in the word line of the device; inducing a third voltage in the first bit line (BLT_(E)), wherein the second voltage is greater than the third voltage. 